ENGINEERING TECHNOLOGY

Beyond the limits of silicon, the two-dimensional transistor is born


“In a ballistic transport transistor, electrons pass through the channel like bullets without being collided, and energy is not lost by scattering, so the higher the trajectory rate, the higher the energy utilization efficiency.” Recently, Qiu Chenguang, a researcher at the School of Electronics of Peking University, explained to China Science News.

As silicon-based chips approach the physical limits of Moore’s Law, science and industry are constantly trying to use a variety of two-dimensional materials to develop better next-generation chips.

Recently, the team of Academician Peng Lianmao and Qiu Chenguang of the School of Electronics of Peking University has developed a ballistic two-dimensional indium selenide (InSe) transistor, which is the world’s fastest and lowest energy consumption two-dimensional semiconductor transistor, and its actual performance exceeds Intel’s most advanced silicon-based transistor. The study was recently published in Nature.

According to reports, the room temperature ballistic rate of the new transistor is as high as 83%, which is much higher than the ballistic rate of silicon-based transistors (less than 60%), and is expected to realize chips with both high performance and low power consumption.

A number of international reviewers believe that this study solves several important challenges in achieving high-performance two-dimensional transistors, is an important milestone in the research of two-dimensional electronic devices, and has important scientific significance.

Targeting “critical bottlenecks”

As the “heart” of the information age, chips provide a steady stream of power for the development of big data and artificial intelligence. The increase in chip speed is due to the scaling of transistors, but silicon-based chips are currently close to the physical limit of Moore’s Law.

The computer industry has been following Moore’s Law, which is to hold twice as many transistors as the previous generation on a given integrated circuit area, doubling its performance. However, practice over the years has shown that while the performance of integrated circuits is improved, negative effects such as the short channel effect are increasing, and the difficulty of integration, energy consumption and cost are also rising.

Two-dimensional semiconductor materials are considered to be the next “outlet” of future chip channel materials.

This atomic-thick material has the advantages of ultra-thin body and high mobility, which has attracted widespread interest from the scientific and industrial communities. In recent years, leading global semiconductor manufacturing companies and research institutions such as Intel, TSMC, Samsung and the European Microelectronics Center have invested in research on 2D materials.

However, due to bottlenecks such as contact resistance and gate media, all 2D transistors have achieved performance comparable to the industry’s advanced silicon-based transistors so far.

Based on more than ten years of research in the field of nanodevices, the team focuses on the underlying core problems and key scientific bottlenecks in the field of two-dimensional electronics, hoping to tap the ultimate potential of two-dimensional semiconductors in the field of electronics and prepare two-dimensional transistors that truly play the intrinsic advantages of low-dimensional materials.

They chose two-dimensional indium selenide as the channel material, a semiconductor material with excellent physical properties that far exceed those of comparable materials. For example, with higher room-temperature carrier mobility (> 2000 cm2/Vs) and smaller electron effective mass (0.14 me), the intrinsic thermal velocity of the material can be higher. According to calculations, its electrical performance is better than almost all currently known N-type semiconductor materials (including conventional silicon semiconductors)

“Theoretically, transistors with two-dimensional indium selenide as channels will have higher limit performance.” Jiang Jianfeng, the first author of the paper and a doctoral student at the School of Electronics of Peking University, told China Science News.

However, how do you make theory a reality? This is not an easy task.

According to reports, TSMC Technology Research Division also lists two-dimensional indium selenide as the most promising N-type semiconductor material. However, due to many experimental challenges, indium selenide transistors with near-limit performance have not yet been achieved.

An international problem in the application of two-dimensional semiconductor materials such as indium selenide is that the contact between such materials and metals will form a “fermi pinning effect”, resulting in large contact resistance, which greatly limits the speed of transistors.

“Ballistic transistors have almost no scattering during ultra-short channel transmission, and the energy is mainly consumed in the metal and semiconductor junctions at the contact, which is also the core bottleneck of extreme difficulty in two-dimensional electronics.” Researcher Qiu Chenguang explained.

Faced with this worldwide problem, the research team explored a new method to achieve ohmic contact in two-dimensional electronic devices by summarizing and investigating the mature structure and strategy of commercial silicon-based transistor contact, that is, solid-state source doping-induced phase transition technology, which took the lead in the world to push the total device resistance of two-dimensional transistors to near the theoretical limit, refreshing to 124 ohms. Micron, to meet the requirements of transistor resistance for future nodes of integrated circuits (220 ohms • microns).

International reviewers spoke highly of this technological innovation. They believe that contact resistance has always been a major bottleneck in the development of two-dimensional semiconductor electronics, and researchers have innovatively developed new methods to overcome this major challenge, achieving record low contact resistance, setting a benchmark for demonstrating high-performance two-dimensional transistors.

Breaking the ultimate “red wall” of silicon-based chips

The International Semiconductor Devices and Systems Roadmap (IRDS) predicts that the limit gate length of silicon-based transistors will stop at 12 nanometers and the operating voltage cannot be less than 0.6 volts. This defines the final level of integration and power consumption at the end of the future silicon-based scaling process.

In line with the development roadmap of silicon-based devices predicted by the industry’s IRDS, researcher Qiu Chenguang said that ballistic two-dimensional indium selenide transistors have broken the four silicon-based “ultimate red walls”.

First, the 2D indium selenide transistor trench length is reduced to 10 nanometers, exceeding the silicon-based limit of 12 nanometers, while maintaining the ideal subthreshold swing range of 75 millivolts, and the device shutdown characteristics exceed Intel’s commercial 10-nanometer node’s silicon-based optimal FinFET transistors. Second, the operating voltage can be reduced to 0.5 volts, exceeding the expected silicon-based limit of 0.6 volts in 2031. At the same time, the gate delay is reduced to 0.32 picoseconds, which is equivalent to a fourfold advantage over the silicon-based limit (1.26 picoseconds). In addition, the power delay product (reduced to 4.32 ×10-29 jouls/micron) is an order of magnitude below the silicon-based limit.

Jiang Jianfeng told China Science News that this means that in the future, large-scale integrated circuits built with indium selenide transistors will have higher performance and processing speed than silicon-based circuits under the condition of several times lower power consumption, and are expected to realize chips with both high performance and low power consumption.

“This is undoubtedly the highest performance two-dimensional transistor to date, illustrating that the true performance of two-dimensional material transistors (not just in theory) has surpassed the most advanced silicon-based transistors.” The paper was evaluated by international reviewers.

Embark on a “new mileage” in electronics

From high hopes from academia and industry to the real development of the world’s fastest and lowest energy-consuming two-dimensional semiconductor transistor to date, this “milestone” breakthrough embodies the research team’s persistent exploration and bold innovation in the four years from 2019 to 2022.

The technological innovation it brings is manifold.

In addition to solving the international problem of total resistance of electronic devices, the research team also innovatively used three-layer indium selenide with high carrier thermal velocity (smaller effective mass) as a channel, achieving a room temperature ballistic rate of up to 83%, which is much higher than that of silicon-based transistors (less than 60%), which is the highest value of current field-effect transistors.

They also solved the problem of growing ultra-thin oxide layers on the surface of two-dimensional materials, and prepared 2.6nm ultra-thin double-gate hafnium oxide, which improved the device transconductance to 6 millisie•microns, which is an order of magnitude more than all two-dimensional devices.

In this regard, the reviewers believe that this study solves multiple challenges in achieving high-performance two-dimensional transistors and is a landmark work in the field of two-dimensional transistor research.

Next, Qiu Chenguang said that the research team will focus on several important research directions of two-dimensional electronics, such as P-type ohmic contact of two-dimensional devices, large-area growth and transfer of wafer-level single crystals of two-dimensional materials, standardized integrated processing technology of two-dimensional devices and their heterogeneous integration with silicon-based and carbon-based, etc., so as to accelerate the development process of two-dimensional material chip technology.

There are four authors in this study, Jiang Jianfeng and Xu Lin, Ph.D., School of Electronics, Peking University, are the first authors, Peng Lianmao and Qiu Chenguang are co-corresponding authors, and the School of Electronics of Peking University is the only unit of the paper. (Source: China Science News, Feng Lifei, Gao Jiawei)

Related paper information:https://doi.org/10.1038/s41586-023-05819-w

Faster, power-efficient low-dimensional semiconductor chips. Photo courtesy of interviewee



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