INFORMATION TECHNOLOGY

China has doubled the integration of the same process device and obtained excellent performance


On December 9, Nature Electronics published papers by Professor Zhou Peng, researcher Bao Wenzhong of the School of Microelectronics of Fudan University, and Wan Jing, researcher of the School of Information Science and Engineering. The researchers designed a wafer-level silicon-based two-dimensional complementary tandem transistor that can double the device integration density and obtain superior electrical performance at the same process node.

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Silicon-based 2D stacked wafer-level fabrication and device structure Photo courtesy of interviewee

Traditional integrated circuit technologies use planarly unfolded electronic and hole-type transistors to form complementary structures to obtain high-performance computing power. The increase in density is mainly achieved by reducing the size of the cell transistor. For example, the industry below the 7nm node uses extreme ultraviolet lithography to achieve high-precision dimensional miniaturization. Extreme ultraviolet lithography equipment is complex, and the value of three-dimensional stacked complementary transistor (CFET) technology that can greatly improve the integration density under the existing technology node is highlighted.

However, the process complexity of all-silicon-based CFET is high and the performance degradation is severe in complex process environments. Therefore, the research and development of CFET devices and integrations that are highly compatible with China’s mainstream technology is of great significance for the independent development of new integrated circuit technologies.

Recently, this technology uses a mature back-end process to integrate new two-dimensional materials on silicon-based chips, and uses the highly matched physical properties of the two to successfully realize a 4-inch large-scale three-dimensional heterogeneous integrated complementary field-effect transistor. The device integration density was doubled at the same process node and excellent electrical performance was obtained. The research team of Fudan University introduced the new two-dimensional atomic crystal into the traditional silicon-based chip manufacturing process to realize wafer-level heterogeneous CFET technology. Compared with silicon materials, the single-atom layer thickness of two-dimensional atomic crystals gives it superior short channel control capabilities in small size devices.

The research team used the standard back-end process of silicon-based integrated circuits to stack molybdenum disulfide (MoS2) on traditional silicon-based chips in three dimensions to form a heterogeneous complementary CFET structure of p-type silicon-n-type molybdenum disulfide. The low-temperature process of molybdenum disulfide is highly compatible with the back-end process of current silicon-based integrated circuits, which greatly reduces the process difficulty and avoids the degradation of the device. At the same time, the carrier mobility of the two materials is close and the device performance is perfectly matched, so that the performance of heterogeneous CFET is better than that of traditional silicon-based and other materials. For example, its inverter gain is as high as 142.3 V/V at 3 V and 1.2 V/V at 0.1 V ultra-low voltage supply with low power consumption of 64 pW. The team also verified the application of the new device in “all-in-one” photoelectric detection and gas sensing.

At present, larger size wafer-level heterogeneous CFET technology based on industrial production lines is under development. This technology will further improve the integration density of chips, meet the development needs of applications such as high-computing power processors, high-density memory and artificial intelligence, and help break the technical blockade of foreign countries in the field of large-scale integrated circuits. (Source: China Science News, Zhang Shuanghu, Huang Xin)

Related paper information:https://doi.org/10.1038/s41928-022-00881-0



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