Important progress has been made in the field of CMOS back-end integration and oxide semiconductors

On September 28, the research group of assistant professor Li Yida of the Shenzhen-Hong Kong School of Microelectronics of Southern University of Science and Technology made important progress in the field of complementary metal oxide semiconductor (CMOS) back-end integration and oxide semiconductor. The results were published in Nature Communications.

As demand for data-driven applications such as next-generation machine learning accelerators and the Internet of Things continues to grow, traditional von Neumann architectures face serious “memory wall” challenges, further exacerbated by the shrinking of silicon-based transistor processes. In order to break through this bottleneck, single-chip three-dimensional integration or in-memory computing that integrates storage units and computing units has become a potential solution. However, silicon-based technologies for CMOS back-end integration are limited by low thermal load (less than 400 degrees Celsius), and these super-silicon devices such as two-dimensional materials and oxide semiconductors are well compatible with CMOS back-end processes.

Oxide semiconductors have the advantages of low process temperature, good transparency, large film growth, high electron mobility, and wide bandgap, which make them suitable for memory-driven circuits and logic circuits based on high-performance thin-film transistors. With increasing interest in implementing new computing architectures with new capabilities and powerful computing power, there is an urgent need to develop high-performance oxide semiconductor transistors to enable monolithic 3D integrated circuits compatible with CMOS back-end processes.

In this study, the research team first used the atomic layer deposition process to achieve a high-performance thin-film transistor (TFT) based on polycrystalline ZnO semiconductors, which has electron mobility of up to 140 square centimeters per volt second, a current switching ratio greater than 108, and a gate leakage current of less than 10 to 11 amps. The TFT is then integrated into a memristor array, enabling a 1T1R storage array with 1 kBit that can be read at high speed. In order to co-design the TFT-based circuit, the research team also modeled the ZnO TFT, based on the device model, and implemented a 5-stage ring oscillator based on a pure NMOS design inverter, which can operate at a frequency of 44.85 MHz. (Source: China Science News, Diao Wenhui)

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Research diagram Courtesy of SUSTech

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