The self-organizing mapping network (SOM, Figure 1a), also known as the “Kohone network,” is a powerful, unsupervised learning neural network inspired by the topology of the brain. Compared with classical linear algorithms such as multidimensional scale or principal component analysis, SOM has more powerful data clustering capabilities, showing unique advantages in clustering and optimization problems such as language recognition, text mining, financial forecasting, and medical diagnosis. However, the implementation of SOM based on traditional CMOS hardware is limited by the complexity of computational similarity and neighborhood determination, and there are problems such as complex circuit structure, large energy area overhead, and lack of accurate calculation of similarity. How to build simple, efficient, and accurate SOM hardware remains a challenge. As a new type of programmable nonvolatile memory device, the cross-array structure of the memristor has the natural advantage of supporting parallel computing and in-memory computing, providing a new way for the hardware implementation of SOM.
Recently, the team of Academician Liu Ming of the Institute of Microelectronics and the team of Professor Liu Qi of Fudan University used the memristor array (Figure 1b&c) to build the weight matrix in the SOM network, and realized the efficient SOM hardware system for the first time. In order to solve the problem of increasing the complexity of the hardware system when the number of neurons and input features in SOM increases, the team proposes a new multi-additional line memristor array architecture (Figure 1d), which divides the memristor array into two parts, one as a data row to store the weight information, and the other part as the sum of the squares of the additional row storage weights. The similarity between input vectors and weight vectors can be achieved in a one-step read operation without the need for normalized weights. Based on this hardware system, the team successfully demonstrated applications such as data clustering, image segmentation, and image compression, and successfully used them to solve the problem of combinatorial optimization (Figure 2). Experimental results show that without affecting the success rate or accuracy, the system has higher energy efficiency and computing throughput compared to the CMOS system. In addition, due to its unsupervised characteristics, the application scenarios are more abundant and more cater to the needs of real life, opening up a new way for the construction of memristor-based intelligent hardware.
Figure 1 SOM schematic and its implementation based on a memristor array. (a) SOM network schematic. (b) Typical I-V curve of the memristor. (c) Optical physical drawing of the 128×64 1T1R memristor array. Schematic of (d) 1T1R memristor array implementing 2D-SOM.
Figure 2 Application of memristor-based SOM system. (a) image processing (segmentation); (b) Solve the combinatorial optimization problem (TSP problem).
The research has been supported by the National Key Research and Development Program, the National Natural Science Foundation of China, the National Major Science and Technology Project, and the Key Scientific Research Project of Zhejiang Province. The research results were published online in Nature Communications under the title “Implementing in-situ Self-organizing Maps with Memristor Crossbar Arrays for Data Mining and Optimization.” Dr. Rui Wang of the Institute of Microelectronics is the first author, Professor Liu Qi of the Institute of Chip and System Frontier Technology of Fudan University and Shi Tuo, associate researcher of the Institute of Microelectronics, are co-corresponding authors. (Source: Institute of Microelectronics, Chinese Academy of Sciences)
Related paper information:https://doi.org/10.1038/s41467-022-29411-4
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