The Peking University team has developed a two-dimensional transistor that exceeds the limit of silicon

Chips provide a steady stream of power for the development of big data and artificial intelligence, and the improvement of chip speed benefits from the scaling of transistors, but the performance of traditional silicon-based field-effect transistors is gradually approaching their intrinsic physical limits. The International Roadmap for Devices and Systems (IRDS) predicts that the limit gate length of silicon-based transistors will stop at 12 nm and the operating voltage cannot be less than 0.6 V, which defines the final level of integration and power consumption at the end of the future silicon-based chip scaling process, so there is an urgent need to develop new channel materials to continue Moore’s Law. Atomic-thick two-dimensional semiconductors have attracted widespread interest from the scientific and industrial communities because of their ultra-thin bodies and high mobility, and as one of the strong candidates for future chip channel materials. In recent years, leading global semiconductor manufacturing companies and research institutions such as Intel, TSMC, Samsung and the European Microelectronics Center have invested in research on 2D materials. However, due to bottlenecks in contact, gate media and materials, the performance achieved by all 2D transistors so far cannot be comparable to the industry’s advanced silicon-based transistors, and their experimental results are far behind theoretical predictions and are not enough to demonstrate the ultimate potential of 2D semiconductors.

Recently, Professor Peng Lianmao and researcher Qiu Chenguang’s research group of Peking University School of Electronics prepared a 10nm ultra-short channel ballistic two-dimensional indium selenide transistor, which for the first time made the actual performance of the two-dimensional transistor exceed Intel’s commercial 10nm node silicon-based Fin transistor, and reduced the operating voltage of the two-dimensional transistor to 0.5 V, which is also the world’s fastest and lowest energy consumption two-dimensional semiconductor transistor so far.

The related research results, titled “Ballistic two-dimensional InSe transistors”, were published online in Nature on March 22, 2023. Jiang Jianfeng and Dr. Xu Lin are the joint first authors, Professor Peng Lianmao and Professor Qiu Chenguang are the co-corresponding authors, and the School of Electronics of Peking University is the only unit of the paper.

This work has achieved three technological innovations: the use of three-layer indium selenide with high carrier thermal velocity (smaller effective mass) as the channel, achieving a room temperature ballistic rate of up to 83%, which is the highest value of field-effect transistors at present, much higher than that of silicon-based transistors (less than 60%); It solved the problem of growing ultra-thin oxide layer on the surface of two-dimensional materials, and prepared 2.6nm ultra-thin double-gate hafnium oxide, which raised the transconductance of the device to 6 mSwarn microns, which exceeded all two-dimensional devices by an order of magnitude. The doping-induced two-dimensional phase transition technology was created to overcome the international problem of gold half-contact in the field of two-dimensional devices, and the total resistance was refreshed to 124 ohms•microns, which met the requirements of transistor resistance (220 ohms•microns) in the future nodes of integrated circuits.

In line with the development roadmap of silicon-based devices predicted by IRDS in the industry, the ballistic two-dimensional indium selenide transistor realized by the Peking University team breaks the four silicon-based ultimate “red walls”: 1) the trench length is reduced to 10 nanometers (exceeding the silicon-based limit of 12 nanometers), while maintaining the ideal subthreshold swing range of 75 millivolts, DIBL is only 20 millivolts/volt, and the device’s shutdown characteristics exceed the silicon-based optimal FinFET technology. 2) The voltage is reduced to 0.5 volts (0.6 volts beyond the 2031 silicon-based limit), turning the device current on from the standard off state of 100 nanoamps/micron to more than 1 mA/micron on state. 3) The gate delay is reduced to 0.32 picoseconds, which is four times superior to the silicon-based limit of 1.26 picoseconds. 4) The power consumption delay product is reduced to 4.32*10-29 joules/micron, which is an order of magnitude lower than the silicon-based limit.

Figure 1 Comparison of ballistic 2D indium selenide transistors with advanced node silicon-based transistors

Figure 2 Switching state characteristics of the device

This work breaks through the key scientific bottleneck that has long hindered the development of two-dimensional electronics, pushes the performance of n-type two-dimensional semiconductor transistors to the theoretical limit for the first time, and is the first to experimentally prove that two-dimensional devices are superior to advanced silicon-based technologies in terms of performance and power consumption, injecting strong confidence and vitality into the development of two-dimensional semiconductor technology.

Figure 3 Outlook: Faster and more power-efficient low-dimensional semiconductor chips

(Source: Science Network)

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